View FL7740-18_8981925.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2016 1 publication order number: february 2018 - rev. 3 fl7740 fl7740 constant - voltage primary- side - regulation pwm controller for p ower factor correction the fl7740 provides accurate cv regulation in the steady state with differentiated dynamic function to minimize overshoot and undershoot of output voltage in line and load transient condition. standby power is less than 0.3 w for smart lighting application and power factor is higher than 0.9 even at half load conditi on when enabling pf optimizer for wide output power scalability. startup time is less than 0.2 sec with built - in high voltage startup circuit and output voltage quickly reaches to the target cv level by loop gain transition technique during startup. various protections such as over load, output diode short, sensing resistor short, output short and output over voltage protection guarantee high system reliability. features ? wide u niversal input range (90 v ac ~ 305 v ac ) ? precise cv regulation in the steady state : < 3 % ? cv regulation in the load transient : < 10 % ? overshoot - less fast hv start up time ( < 0.2 sec ) ? low standby power ? pf higher than 0.9 at high - line and half load by pf optimizer ? pulse - by - pulse current limit ? output short protection ? output over voltage protection ? output diode short protection ? sensing resistor short & open protection ? over load protection typical applications ? led lighting system ? ac - dc adapters, tvs, monitors ? off line appliances requiring power factor correction www. onsemi.com so 10 l nb marking diagram zxykk z = plant code x = 1 digit year code y = 1 digit week code kk = 2 digit lot traceability code m = package code a = product version fl 7740 ma pin connections vdd gnd gate cs vs hv nc comv bias pf ordering information see detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet.
fl7740 www. onsemi.com 2 fl 7740 gate gnd vs bias vdd comv nc hv cs pf secondary dc-dc converter dimming control module dimming signal v ac v out.main v out.bias 0-10, dali, wireless, etc. figure 1 . application schematic comv vs hv cs vdd jfet gm amp. v eav v ref dynamic control gain control at startup bias pf 5v regulator digital pf optimizer c pf detector v dyn-ref control protection gate vdd eav shutdown v out open/short protection r cs open/short protection over current protection over load protection thermal shutdown v in.pk digital duty control nc gnd driver v dyn-ref1,2,3 s/h figure 2 . simplified block diagram
fl7740 www. onsemi.com 3 pin function description pin no. pin name function description 1 vdd ic supply ic operating current and mosfet driving current are supplied using this pin. 2 gnd g round controller ground pin. 3 gate pwm driver output this pin uses the internal totem - pole output driver to drive the power mosfet. 4 cs current sense connected to a current sense resistor to detect the mosfet current for pulse - by - pulse current limit. 5 vs voltage sense this pin is connected to the auxiliary winding of the transformer via a resistor divider to detect the output voltage. 6 pf power factor this pin is connected to a resistor to optimize power factor. 7 bias internal circuit bias bypass pin for the internal supply, which powers all control circuitry on the ic. 8 comv loop compensation this pin is connected to a capacitor between comv and gnd for compensation. 9 nc no connection 10 hv high voltage this pin is connected to the rectified input voltage via a resistor for fast startup.
fl7740 www. onsemi.com 4 maximum ratings (note 1 ) 1. stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, devi ce functionality should not be assumed, damage may occur and reliability may be affected . 2. refer to electrical characteristi c s , recommended operating ranges and /or application information for safe operating parameters . 3. this device series incorporates esd protection and is tested by the following methods: es d human body model tested per aec - q100 - 002 (eia/jesd22 - a114) esd machine model tested per aec - q100 - 003 (eia/jesd22 - a115) latchup current maximum rating: 150 ma per jedec standard: jesd78 recommended operating ranges (note 4 ) 4. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recommended operating ranges limits may affect device reliability. rating symbol value unit hv pin voltage range v hv(max) 560 v vdd, gate pin voltage range v mv(max) - 0.3 to 30 v comv, pf, bias, vs, cs pin voltage range v lv(max) - 0.3 to 6 v vs, cs pin negative pulse voltage at i lv < 0.2 a and t pulse < 300 ns v lv(pulse ) - 1.5 v maximum power dissipation (t a < 50c) p d(max) 663 mw maximum junction temperature t j(max) 150 c storage temperature range t stg - 5 5 to 150 c junction - to - ambient thermal impedance r 3 ) esd hbm 2 kv esd c apability, charged device model (note 3 ) esd cdm 2 k v rating symbol min max unit ambient temperature t a - 40 125 c
fl7740 www. onsemi.com 5 electrical characteristics v dd = 18 v and t j = - 40 ~ 125 c unless otherwise specified parameter test conditions symbol min typ max unit vdd section turn - on threshold voltage v dd-on 14.5 1 6.0 17.5 v turn - off threshold voltage v dd- off 6.75 7.75 8.75 v operating current c load = 1 nf , v dd = 18v i dd-op 3 5 6.5 ma operating current during auto restart i dd-ar 0.3 1 m a v dd over - voltage - protection v dd-ov p 24 2 5 2 6 v v bias voltage v bias 4.85 5.00 5.15 v gate section output voltage low v ol 0.2 v output voltage high v dd = 18 v v oh 17.8 v peak sourcing curren t design guaranteed c load = 1 nf, v dd = 20 v c load = 1 nf, v dd = 23 v i source 180 210 ma peak sinking curren t design guaranteed c load = 1 nf, v dd = 20 v c load = 1 nf, v dd = 23 v i sink 385 435 ma rising time c load = 1 nf t r 1 10 150 190 ns falling time c load = 1 nf t f 4 0 60 80 ns hv section supply current from hv pin v hv = 5 6 0 v, v dd = 0 v i hv 3 9 ma leakage current after startup i hv -lc 1 10 a jfet regulation time at startup design guaranteed t r - jfet 400 500 600 ms v dd high limit during jfet regulation v dd- jfet -hl 17.5 19.0 20.5 v v dd low limit during jfet regulation v dd- jfet -ll 15.5 17.0 18.5 v pwm section min. turn - on time min. limit design guaranteed t on - min - min 0.40 s min. turn - on time max. limit design guaranteed t on - min -max 2.0 s max. turn - on time design guaranteed t on -max 23.3 s oscillator section max. frequency f max 60 65 70 khz min. frequency f min 0.72 0.80 0.88 khz current sense section leading - edge blanking tim e design guaranteed t leb 300 ns propagation delay to gate design guaranteed t pd 50 100 150 ns voltage sense section t dis blanking time at vs samplin g design guaranteed t dis - bnk 0.95 1.00 1.05 s vs clamping voltage i vs =1 ma i vs =10 a v vs- clamp - 0.1 0.35 v feedback section reference voltage v ref 3.465 3.5 3.535 v
fl7740 www. onsemi.com 6 electrical characteristics (continued) v dd = 18 v and t j = - 40 ~ 125 c unless otherwise specified parameter test conditions symbol min typ max unit cv regulation tolerance v vs = 3.5 v , t j = 25 c v vs = 3.5 v, t j = - 40~1 25 c cv regulation - 0.7 - 1.2 +0.7 +1.2 % transconductance g m 1 6 20 2 4 mho comv sink current v vs = 4 v i comv - sink 8 1 0 12 a comv source current v vs = 3 v i comv - source 8 1 0 12 a comv high voltag e v comv - hgh 4. 7 v comv low voltag e v comv - low 0. 1 v start sequence section soft start time design guaranteed t soft - start 25.6 ms ss1 minimum time design guaranteed t ss1 - min 2 ms ss1 maximum time design guaranteed t ss1 -max 100 ms ss21 time design guaranteed t ss21 45 ms ss22 maximum time design guaranteed t ss22 30 ms dynamic section dyn reference set threshold v dyn - ref - set 0.72 0.80 0.88 v dyn reference set t ime design guaranteed t dyn - ref - set 5 s ov reference 5 design guaranteed v o v- ref 5 + 20 % ov reference 4 v o v- ref4 +14 +15 +16 % ov reference 3 v ov - ref3 +9 +10 +11 % ov reference 2 v ov - ref2 +4.7 +5.7 +6.7 % ov reference 1 v ov - ref1 +1.86 +2.86 +3.86 % uv reference 1 v uv - ref1 - 3.86 - 2.86 - 1.86 % uv reference 2 v uv - ref2 - 6.7 - 5.7 - 4.7 % uv reference 3 design guaranteed v uv - ref3 - 10 % protection section auto restart delay time design guaranteed t ar 3 s vs ouptut short h ys . v oltage 'h' v vs- os -h 0.85 0.90 0.95 v vs ouptut short h ys . v oltage ' l ' v vs- os -l 0.65 0.70 0.75 v osp delay time design guaranteed t osp - delay 35 ms high current limit threshold v cs - high -cl 1.1 3 1.20 1.2 7 v low current limit threshold v cs - low -cl 0.15 0.20 0.25 v over current protection voltage v cs - ocp 1.8 v cs threshold voltage for srsp v cs - srsp 0.0 40 0.075 0.125 v max. turn - on time for srsp i vs = 100 ua i vs = 700 ua t ton -max - srsp 7.5 1. 3 10.0 1. 6 12.5 1.9 s threshold temperature for otp design guaranteed t otp 150 o c junction temperature hysteresis design guaranteed t otp -h ys 30 o c
fl7740 www. onsemi.com 7 typical characteristic s 12 13 14 15 16 17 18 19 20 - 40 - 20 0 20 40 60 80 100 120 140 tj , junction temperature (oc) v dd-on (v) figure 3 v dd - on vs. temperatur e 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 - 40 - 20 0 20 40 60 80 100 120 140 figure 4 v bias vs. temperatur e 6.50 6.75 7.00 7.25 7.50 7.75 8.00 8.25 8.50 8.75 9.00 - 40 - 20 0 20 40 60 80 100 120 140 - figure 5 v dd - off vs. temperatur e 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 - 40 - 20 0 20 40 60 80 100 120 140 - - figure 6 v cs - high - cl vs. temperatur e 3.40 3.42 3.44 3.46 3.48 3.50 3.52 3.54 3.56 3.58 3.60 - 40 - 20 0 20 40 60 80 100 120 140 figure 7 v ref vs. temperatur e 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 - 40 - 20 0 20 40 60 80 100 120 140 - figure 8 v cs - ocp vs. temperatur e
fl7740 www. onsemi.com 8 typical characteristic s tj, junction temperature (oc ) cv regulation (%) - 1.0 - 0.8 - 0.6 - 0.4 - 0.2 0.0 0.2 0.4 0.6 0.8 1.0 - 40 - 20 0 20 40 60 80 100 120 140 figure 9 cv regulation vs. temperatur e 9.5 9.6 9.7 9.8 9.9 10.0 10.1 10.2 10.3 10.4 10.5 - 40 - 20 0 20 40 60 80 100 120 140 -3 figure 10 v ov - ref3 vs. temperatur e 2.10 2.25 2.40 2.55 2.70 2.85 3.00 3.15 3.30 3.45 3.60 - 40 - 20 0 20 40 60 80 100 120 140 -1 figure 11 v ov - ref1 vs. temperatur e - 3.60 - 3.45 - 3.30 - 3.15 - 3.00 - 2.85 - 2.70 - 2.55 - 2.40 - 2.25 - 2.10 - 40 - 20 0 20 40 60 80 100 120 140 -1 figure 12 v uv - ref1 vs. temperatur e 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 6.1 6.2 - 40 - 20 0 20 40 60 80 100 120 140 -2 figure 13 v ov - ref2 vs. temperatur e - 6.2 - 6.1 - 6.0 - 5.9 - 5.8 - 5.7 - 5.6 - 5.5 - 5.4 - 5.3 - 5.2 - 40 - 20 0 20 40 60 80 100 120 140 -2 figure 14 v uv - ref2 vs. temperatur e
fl7740 www. onsemi.com 9 application information general fl7740 is high power factor flyback controller with accurate primary side constant voltage regulation fo r smart led lighting and ac - dc adapter, tv & monitors application. precise output voltage detection and dynamic function manage good cv regulation. startup is fast with internal hv biasing circuit with overshoot - less gain control. it guarantees high system reliable protection functions such as output over vo ltage, output short, over load, over current and thermal shut down protections. constant voltage regulation vs pin detects output voltage information (= v eav ) during secondary side diode conduction time and internal gm amplifier regulates the detected volt age at 3.5 v. dynamic response at load transient at load transient condition, v eav is shortly out of regulation due to the narrow pfc loop bandwidth. when v eav is far from 3.5 v regulation reference, duty is quickly changed to bring the v eav back to 3.5 v by dynamic control function. hv biasing at s tartup internal hv biasing circuit quickly charges external vdd capacitor to begin ic operation at plug - in. after 500 ms initial time, hv biasing stops for low standby power. overshoot - less gain control at startup once ic operation starts, feedback loop is dominantly controlled in proportional gain to speed up the output capacitor charging. once output voltage is settled down close to the regulation target, gain control is smoothly cha nged to integration gai n with no output voltage overshoot. digital pf optimizer fl7740 compensates input current phase shift caused by emi filter capacitor current in a half line period. with sophisticated digital pf optimizer, fl7740 significantly improves power factor in the wide load range. pulse -by - pulse current limit w h en cs pin voltage reaches to 1.2 v current limit reference, gate turn - on is terminated to limit primary peak current. auto restart at protection once protection is triggered, ic operation stops for 3 sec and begin the operation for auto restart. output short protection when v eav is less than 0.7 v continuously for 35 ms, output short protection is triggered . o utput over voltage protection when v eav is higher than v vs -ovp threshold or vdd is higher than v dd -ovp , output over voltage protection is triggered . output diode short protection once output diode is short circuited, high di/dt in the primary winding is occurred by leakage inductance. once cs pin voltage reaches to 1.7 v, switching is shut down . se nsing resistor short protection at first switching, sensing resistor short condition is monitored by detecting cs pin voltage. if cs is less than 75 mv during first gate turn - on time, sensing resistor short protection is triggered. over load protection wh en output is over loaded, pulse - by - pulse current limit event is occurred. if this event lasts for 60 half line cycles, over load protection is triggered . thermal shut down if internal junction temperature is higher than 150 o c, protection is triggered and released with 30 o c hysteresis.
fl7740 www. onsemi.com 10 primary side constant voltage regulation fl7740 utilizes auxiliary winding to detect output voltage during secondary side diode conduction time (=t dis ) . the true output voltage level without secondary diode forward voltage drop is at the end of secondary diode conduction time. in order to detect the right output voltage, 85% of t dis at previous switching cycle is sampling time for v eav detection at current switching cycle. s / h vs v ref error amp . v eav comv t dis detection duty control n aux v in . pk figure 15 . primary side regulation vs gate 85% t dis at previous switching t dis v eav sampling figure 16 . v eav detection the sampled v eav is compared with 3.5 v v ref at th e input of the error amplifier. several hundreds nf capacitor is connected to t he output of the error amplifier at comv pin to keep feedback loop slow in pfc control . comv voltage controls duty to regulate v eav same as v ref in the system. turn - on time is controlled by both comv voltage and v in.pk information in line feedforward operation in order to keep the constant comv voltage in the wide input voltage range. so, turn - on time is proportional to comv voltage and inversely proportional to v in.pk . startup after plug - in, external vdd capacitor is quickly charged by internal hv biasing supply. even after vdd is higher than 16 v v dd-on , internal hv biasing is still enabled for 500 ms, so hv biasing can relieve vdd capacitor discharging until auxiliary windin g builds up vdd voltage . in order to speed up large output capacitor charging without overshoot, fl7740 starts with proportional gain during startu p sequence (ss1 + ss2) by using internal resistive load at the output of the error amplifier. in ss1, ccm prevent operation is enabled for the initial 2 ms. when output voltage is 0 v, deep ccm could be entered at initial startup and cs could touch ocp level with startup failure. so, pulse - by - pulse current limit is 0.2 v and switching frequency is 22 khz durin g the 2 ms ccm prevent time. also, duty is gradually increased for 26 ms fo r soft startup. once 5 v pulled - up comv voltage drops less than 4.5 v as v eav is close to v ref , ss1 is ended. maximum ss1 time is limited up to 100 ms. in ss2, v comv drops from 5 v and goes into p - gain steady state in which v eav is little bit lower than v ref due to the error amplifier input error in p - gain. once p - gain steady state is settled down in 45 ms, ss2 is finished at min. v comv ra nge not to make overshoot when transitionin g to i - gain after ss2. fl7740 ends ss2 by monitoring v in 1.5 ms after v in.pk detection moment where v comv is generally in the min. range. v comv duty v eav v in v ref startup time by p - gain i - gain 45 ms 4 . 5 v 26 ms soft start 2 ms ccm prevent 5 . 0 v v in . pk 1 . 5 ms ss 1 ss 2 figure 17 . startup sequence dynamic cv regulation d u e to the narrow loop bandwidth, pfc controller generally d oes not guarantee good cv regulation at load transient. especially in secondary side regulation, primary side controller does not know the outpu t voltage level and it only monitors the output of feedback signal through opto - coupler. therefore, output voltage undershoot is severely happened at no to full load transient in the conventional ssr pfc control. in order to overcome this, fl7740 utilizes the benefit of psr with on semicond uctor ? s proprietary dynamic duty control by monitoring the output voltage . for example, when v eav is less than v uvd.en (under voltage dynamic enable threshold), duty is quickly increased not to allow undershoot anymore. once v eav rises higher than v uvd.dis (under voltage dynamic disable threshold), duty quickly drops and follows comv voltage. during the v eav hiccup operation, comv voltage slowly increases and dynamic operation is terminated when comv voltage is close to steady state level.
fl7740 www. onsemi.com 11 v ref gm amp. v eav comv v ovd.en2 over voltage dynamic (ovd) under voltage dynamic (uvd) v ovd.en1 v uvd.en v uvd.dis duty generator v ovd.dis gate figure 18 . dynamic function block v ref v eav v comv v uvd.en v uvd.dis duty figure 19 . no to full load transient v ref v eav v comv v ovd.en1 v ovd.dis duty v ovd.en2 figure 20 . full to no load transient in case of ovd (over voltage dynamic) function, it has two enable levels (v ovd.en 1 and v ovd .en2 ). if output voltage overshoot at load transient is too high, v eav increases to v ovd.en 2 passing by v ovd .en 1 . d uty quickly drops when reaching v ovd.en1 and drop s to min. level at once not to allow severe output over voltage when v eav increases higher than v ovd .en2 . fl7740 provides two sets of dynamic triggering threshold. when user prefers narrow output voltage variation at load transient with large output capac itor, set0 can be selected without capacitor at pf pin. if wider output voltage variation is allowed and output capacitor should be small due to system size, set1 can be selected with connection of capacitor around 0.5 n f at pf pin. fl7740 detects capacita nce at pf pin at the beginning of switching startup and maintains the set# until uvlo is triggered. during the 1st switching, pf pin is pulled down to 0 v. in the 2nd switching, pf pull down is disabled and pf voltage is monitored 5 us after 2nd switching period begins. if the pf voltage is higher than 0.8 v v dyn-ref - set , set0 is decided. if not, set1 is determined . dynamic threshold at set0 and set1 v vs.ovp v ovd.en2 v ovd.en1 v ovd.dis v uvd.dis v uvd.en v ov - ref 5 +20 %v ref set1 v ov - ref4 +15%v ref set0 set1 v ov - ref 3 +10 %v ref set0 set1 v ov - ref 2 +5.7 %v ref set0 set1 v ov - ref 1 +2.9 %v ref set0 v u v - ref 1 - 2.9 %v ref set0 v u v - ref 2 - 5.7 %v ref set1 set0 v u v - ref 3 - 10%v ref set1 digital pf optimizer as line voltage increases and output load decreases, pf is degraded due to the effect of emi filter capacitor charging/discharging current. input current is the sum of emi filter capacitor current and flyback input current. whether the flyback input current is exactly in - phase sinusoidal current with line voltage, 90 o phase shifted emi filter cap current worsens displacement factor of the overall system input current. the on semiconductor? s proprietary pf optimizer accurately compensates the emi filter capacitor current and improves pf more than 0.1 at high line and half load condition. the calculation coefficient in the pf optimizer is externally programmable by supplying a certain level of voltage at pf pin with external resistive divider from 5 v
fl7740 www. onsemi.com 12 bias pin . before 1 st switching, fl7740 converts the pf voltage into digital value without switching noise and keeps the digital value for the coefficient until uvlo is triggered. recommended v pf is in equation 1, where l m is magnetizing inductance and c emi is total emi filter capacitance. 1.5 10 5 v 9 pf + = emi m c l (eq. 1) as v pf increases, the coefficient in the pf optimizer calculation is larger with better pf, but thd is worse due to the input current distortion at input voltage zero cross . therefore, v pf adjustment by changing pf resistors is recommended to bring the best pf and thd performance to meet user ? s target. when v pf is lower than 1.5 v, pf optimizer is disabled. i emi.cap i flyback v in i in gate t on ideal i in figure 21 . with pf optimizer v in i in gate t on i emi.cap i flyback (=ideal i in ) leading phase figure 22 . without pf optimizer protection ? auto - restart once protection is triggered, fl7740 terminates switching and internal 3 sec counter make s delay time. in 3 sec, vdd voltage is regulated between 17 v and 19 v by internal hv biasing not to fall in uvlo. after 3 sec, vdd falls down to 7.75 v v dd- off and ic is reset with released protection . when vdd voltage is up again to 16 v v dd-on , fl7740 begins startup se quence. vdd gate 19 v 17 v 7.75 v 16 v protection triggered vdd regulation for 3 sec ic reset ic restart figure 23 . auto restart ? output over voltage protection output over voltage is hardly triggered due to the powering limit by dynamic function. but, in the abnormal condition, output ovp is triggered when v eav is higher than 4.0 v @ set0 / 4.2 v @ set1 for 4 switching cycles or vdd voltage is higher than 25 v for 10 us delay. ? output short protection at output short condition, v eav is less than 0.7 v. if this condition lasts for continuous 35 ms switching time, osp is triggered. ? over current protection when cs voltage is higher than 1.8 v over the 1.2 v pulse - by - pulse current limit, protection is immediately triggered. oc p protects output diode short, sensing resistor open and transformer saturation condition. ? sensing resistor short protection 1 st switching is 0.2 v current mode. if cs doesn ? t reach over 75 mv threshold during 1 st turn - on tim e, srsp is triggered. max. turn - on time at 1 st switching is inversely p roportional to input volt age to limit the primary peak current. ? over load protection at over load condition, cs reaches to 1.2 v pulse - by - pulse current limit. fl7740 generates internal zc (zero cross) signal and olp is triggered if the event (1.2v current limit event between the two close zc si gnals) is occurred for consecutive 60 zc signals. v in cs zc olp 1.2 v current limit event 1 0 0 2 3 58 57 59 60 olp count figure 24 . over load protection ? thermal shut down when internal junction temperature is higher than 150o c, tsd is triggered and protection is release d when the junction temperature drops under 120 o c.
fl7740 www. onsemi.com 13 ac input secondary dc-dc converter mcu module dimming signal pg (power gnd) sg (signal gnd) fl7740 gate vs bias vdd comv nc hv cs pf gnd pg line goes under r hv1 g d s r hv1 r gate cs line goes under r gate r hv2 vdd line goes under r hv2 r hv3 sg line goes under r hv3 1 2 3 4 5 g-gate and s-gnd distance should be short. sg and pg are connected close at gnd pin. comv,bias,pf,vs circuit ground and aux. winding vdd circuit ground are connected close at gnd pin. smd filter cap is connected close at vdd and gnd pin. powering lines (drain and pg) are closely placed and away from fl7740 control circuits. 1 2 3 4 5 bridge diode single layer pcb layout guidance ordering information device package shipping fl7740mx 10 lead soic, jdec ms - 012, 150? narrow body tape and reel
fl7740 package dimensions on semiconductor and the on semiconductor logo are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries in the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and o ther intellectual property. a listing of on semiconductor?s product/pate nt coverage may be accessed at www.onsemi.com/site/pdf/patent - marking.pdf. on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suit ability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, cons equential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, incl uding compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications informa tion provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ? typicals? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the rights of others. on semiconductor products are not designed, int ended, or authorized fo r use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, dam ages, and exp enses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, ev en if such claim alleges that on semiconductor was negligent regarding the design or ma nufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to al l applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 - 675 - 2175 or 800 - 344 - 3860 toll free usa/canada fax: 303 - 675 - 2176 or 800 - 344 - 3867 toll free usa/canada email : orderlit@onsemi.com n. american t echnical support : 800 - 282 - 9855 toll free usa/canada. europe, middle east and africa technical support : phone: 421 33 790 2910 japan customer focus center phone: 81 - 3 - 5817 - 1050 on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of FL7740-18

	To Download FL7740-18 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .